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true accuracy, 16-bit 12 v/15 v, serial input voltage output dac ad5570 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features full 16-bit performance 1 lsb maximum inl and dnl output voltage range up to 14 v on-board reference buffers, eliminating the need for a negative reference controlled output during power-on temperature ranges of ?40c to +85c for a/b version/?40c to +125c for w/y version settling time of 10 s to 0.003% clear function to 0 v asynchronous update of outputs ( ldac pin) power-on reset serial data output for daisy chaining data readback facility 5 kv hbm esd classification applications industrial automation automatic test equipment process control data acquisition systems general-purpose instrumentation functional block diagram v out v dd dgnd ad5570 refin refgnd ldac sdin clr sclk sync pd dac register shift register power-down control logic power-on reset sdo v ss 2r agnd agnds r r 16-bit dac 0 3760-001 figure 1. general description the ad5570 is a single 16-bit serial input, voltage output dac that operates from supply voltages of 11.4 v up to 16.5 v. integral linearity (inl) and differential nonlinearity (dnl) are accurate to 1 lsb. during power-up, when the supply voltages are changing, v out is clamped to 0 v via a low impedance path. the ad5570 dac comes complete with a set of reference buffers. the reference buffers allow a single, positive reference to be used. the voltage on refin is gained up and inverted internally to give the positive and negative reference for the dac core. having the reference buffers on-chip eliminates the need for external components such as inverters, precision amplifiers, and resistors, thereby reducing the overall solution size and cost. the ad5570 uses a versatile 3-wire interface that is compatible with spi?, qspi?, microwire?, and dsp? interface standards. data is presented to the part as a 16-bit serial word. serial data is available on the sdo pin for daisy-chaining purposes. data readback allows the user to read the contents of the dac register via the sdo pin. features on the ad5570 include ldac which is used to update the output of the dac. the device also has a power-down pin ( pd ), allowing the dac to be put into a low power state, and a clr pin that allows the output to be cleared to 0 v. the ad5570 is available in a 16-lead ssop. product highlights 1. 1 lsb maximum inl and dnl. 2. buffered voltage output up to 14 v. 3. output controlled during power-up. 4. on-board reference buffers. 5. wide temperature range of ? 40c to +125c. 6. 5 kv hbm esd classification.
ad5570 rev. c | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing characteristics..................................................................... 5 standalone ..................................................................................... 5 timing characteristics..................................................................... 6 daisy-chaining and readback ................................................... 6 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 terminology .................................................................................... 10 typical performance characteristics ........................................... 11 general description ....................................................................... 16 dac architecture....................................................................... 16 reference buffers........................................................................ 16 serial interface ............................................................................ 16 transfer function....................................................................... 17 clear ( clr ) ................................................................................. 17 power-down ( pd ) ..................................................................... 17 power-on reset.......................................................................... 17 serial data output (sdo)......................................................... 17 applications information .............................................................. 19 typical operating circuit ......................................................... 19 layout guidelines....................................................................... 20 opto-isolators............................................................................. 20 microprocessor interfacing....................................................... 21 evaluation board ........................................................................ 22 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 11/10rev. b to rev. c added hbm esd classification to features and product highlights section ............................................................................ 1 added esd parameter to table 4 ................................................... 8 changes to ordering guide .......................................................... 24 9/06rev. a to rev. b updated format..................................................................universal changes to table 3............................................................................ 6 changes to figure 43...................................................................... 21 changes to ad5570 to 8xc51 interface section ........................ 21 changes to ordering guide .......................................................... 24 4/05rev. 0 to rev. a changes to table 1............................................................................ 3 changes to table 4............................................................................ 8 added figure 16.............................................................................. 12 revision 0: initial version
ad5570 rev. c | page 3 of 24 specifications v dd = +11.4 v to +16.5 v, v ss = ?11.4 v to ?16.5 v, v ref = 5 v, refgnd = agnd = dgnd = 0 v, r l = 5 k, c l = 200 pf to agnd; all specifications t min to t max , unless otherwise noted. table 1. parameter 1 min typ 2 max unit test conditions/comments accuracy resolution 16 bits monotonicity 16 bits differential nonlinearity (dnl) ?1 0.3 +1 lsb relative accuracy (inl) b/y grade ?1 0.4 +1 lsb a/w grade ?2 0.6 +2 lsb positive inl drift over time 3 see figure 16 a/b grades 2.5 ppm w/y grades 6.5 ppm negative full-scale error 0.9 7.5 mv full-scale error 1.8 6 mv bipolar zero error 0.9 7.5 mv gain error 1.8 7.5 mv gain temperature coefficient 4 +0.25 1.5 ppm fsr/c reference input reference input range 4 4 5 5 v with 11.4 v supplies 4 5 7 v with 16.5 v supplies input current 0.1 a output characteristics 4 output voltage range v ss + 1.4 v dd ? 1.4 v with 11.4 v supplies v ss + 2.5 v dd ? 2.5 v with 16.5 v supplies output voltage settling time 12 16 s at 16 bits to 0.5 lsb 10 13 s to 0.0003% 6 7 s 512 lsb code change slew rate 6.5 v/s measured from 10% to 90% digital-to-analog glitch impulse 15 nv-s 12 v supplies; 1 lsb change around the major carry bandwidth 20 khz short circuit current 25 ma output noise voltage density 85 nv/hz f = 1 khz; midscale loaded dac output impedance 0.35 0.5 digital feedthrough 0.5 nv-s warmup time 5 12 sec logic inputs input currents 0.1 a v inh , input high voltage 2 v v inl , input low voltage 0.8 v c in , input capacitance 3 pf logic outputs v ol , output low voltage 0.4 v i sink = 1 ma floating-state output 8 pf
ad5570 rev. c | page 4 of 24 parameter 1 min typ 2 max unit test conditions/comments power requirements v dd /v ss 11.4 16.5 v i dd 4 5 ma v out unloaded i ss 3.5 5 ma v out unloaded power-down current 16 a v out unloaded power-supply sensitivity 6 0.1 lsb/v 15 supplies 10%; full-scale loaded power dissipation 100 mw v out unloaded 1 temperature ranges: a and b vers ions = ? 40c to +85c; w and y versions = ? 40c to +125c. 2 typical specifications at 12 v/15 v, +25c. 3 these numbers are generated from the life test of the part. 4 guaranteed by design. 5 warmup time is required for the device to reach thermal equilibrium, thus ac hieving rated performance. 6 sensitivity of negative full-scale error and positive full-scale error to v dd , v ss variations.
ad5570 rev. c | page 5 of 24 timing characteristics standalone v dd = +12 v 5%, v ss = ?12 v 5% or v dd = +15 v 10%, v ss = ?15 v 10%, v ref = 5 v, refgnd = agnd = dgnd = 0 v, r l = 5 k, c l = 200 pf to agnd; all specifications t min to t max , unless otherwise noted. table 2. parameter 1 , 2 limit at t min , t max unit description f max 10 mhz max sclk frequency t 1 100 ns min sclk cycle time t 2 35 ns min sclk high time t 3 35 ns min sclk low time t 4 10 ns min sync to sclk falling edge setup time t 5 35 ns min data setup time t 6 0 ns min data hold time t 7 45 ns min sclk falling edge to sync rising edge t 8 45 ns min minimum sync high time t 9 0 ns min sync rising edge to ldac falling edge t 10 50 ns min ldac pulse width t 11 0 ns min ldac falling edge to sync falling edge (no update) t 12 0 ns min ldac rising edge to sync rising edge (no update) t 13 20 ns min clr pulse width 1 all parameters guaranteed by design and characterization. not production tested. 2 all input signals are measured with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il +v ih )/2. db15 db0 sclk sync sdin ldac 1 clr ldac 2 notes 1 asynchronous ldac update mode. update on falling edge of ldac. 2 synchronous ldac update mode. update on rising edge of sync. t 3 t 2 t 5 t 6 t 7 t 9 t 1 t 4 t 8 t 12 t 11 t 10 t 13 03760-002 figure 2. serial interface timing diagram
ad5570 rev. c | page 6 of 24 timing characteristics daisy-chaining and readback v dd = +12 v 5%, v ss = ? 12 v 5% or v dd = +15 v 10%, v ss = ? 15 v 10%, v ref = 5 v, refgnd = agnd = dgnd = 0 v, r l = 5 k, c l = 200 pf to agnd; all specifications t min to t max , unless otherwise noted. table 3. parameter 1 , 2 limit at t min , t max unit description f max 2 mhz max sclk frequency t 1 500 ns min sclk cycle time t 2 200 ns min sclk high time t 3 200 ns min sclk low time t 4 10 ns min sync to sclk falling edge setup time t 5 35 ns min data setup time t 6 0 ns min data hold time t 7 45 ns min sclk falling edge to sync rising edge t 8 45 ns min minimum sync high time t 9 0 ns min sync rising edge to ldac falling edge t 10 50 ns min ldac pulse width t 14 3 200 ns max data delay on sdo 1 all parameters guaranteed by design and characterization. not production tested. 2 all input signals are measured with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il +v ih )/2. sdo; r pullup = 5 k, c l = 15 pf. 3 with c l = 0 pf, t 14 = 100 ns. sclk sync sdin db15 (n) db15 (n) db0 (n) db0 (n) db15 (n + 1) db15 (n + 1) db0 (n + 1) ldac 1 sdo ldac 2 notes 1 asynchronous ldac update mode. 2 synchronous ldac update mode. t 1 t 8 t 10 t 2 t 3 t 4 t 6 t 5 t 9 t 7 t 14 03760-003 figure 3. daisy-chai ning timing diagram
ad5570 rev. c | page 7 of 24 sclk sync sdin sdo ldac db15 (n) db0 (n) db0 (n) db14 (n) db15 (n) db15 (n + 1) db0 (n + 1) t 2 t 3 t 6 t 5 t 7 t 9 t 1 t 10 t 14 t 8 t 4 03760-004 figure 4. readback timing diagram
ad5570 rev. c | page 8 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to agnd, agnds, dgnd ?0.3 v to +17 v v ss to agnd, agnds, dgnd +0.3 v to ?17 v agnd, agnds to dgnd ?0.3 v to +0.3 v refgnd to agnd, adnds ?0.3 v to +0.3 v refin to agnd, agnds ?0.3 v to +17 v refin to refgnd ?0.3 v to +17 v digital inputs to dgnd ?0.3 v to v dd + 0.3 v v out to agnd, agnds v ss ? 0.3 v to v dd + 0.3 v sdo to dgnd ?0.3 v to +6.5 v operating temperature range w/y grades ?40c to +125c a/b grades ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature (t j max) 150c 16-lead ssop package power dissipation (t j max C t a )/ ja ja thermal impedance 139c/w lead temperature (soldering, 10 sec) 300c ir reflow, peak temperature 230c esd 1 5 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 hbm classification.
ad5570 rev. c | page 9 of 24 pin configuration and fu nction descriptions v ss 1 v dd 2 clr 3 ldac 4 sync 5 sclk 6 sdin 7 sdo 8 refgnd refin refgnd v out agnds 16 15 14 13 12 agnd pd dgnd 11 10 9 ad5570 top view (not to scale) 03760-005 figure 5. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 v ss negative analog supply voltage. ?12 v 5% to ?15 v 10% for specified performance. 2 v dd positive analog supply voltage. 12 v 5% to 15 v 10% for specified performance. 3 clr level sensitive, active low input. a falling edge of clr resets v out to agnd. the contents of the registers are untouched. 4 ldac active low control input. transfers the contents of the input register to the dac register. ldac can be tied permanently low, enabling the outputs to be updated on the rising edge of sync . 5 sync active low control input. this is the fram e synchronization signal for the data. when sync goes low, it powers on the sclk and sdin buffers and enables the input shift re gister. data is transferred in on the falling edges of the following 16 clocks. 6 sclk serial clock input. data is clocked into the input register on the falling edge of the serial clock input. data can be transferred at rates of up to 8 mhz. 7 sdin serial data input. data is cl ocked into the 16-bit register on the falling edge of the serial clock input. 8 sdo serial data output. can be used for da isy-chaining a number of devices together or for reading back the data in the shift register for diagnostic purposes. this is an ope n-drain output; it must be pulled to logic high with an external pull-up resistor of ~5 k. 9 dgnd digital ground. ground reference for all digital circuitry. 10 pd active low control input. allows the dac to be put into a power-down state. 11 agnd analog ground. ground reference for all analog circuitry. 12 agnds analog ground sense. this is normally tied to agnd. 13 v out analog output voltage. 14, 16 refgnd reference ground. tie this pin to 0 v. 15 refin voltage reference input. this is internally buffered before being applied to the dac. for bipolar 10 v output range, refin is 5 v.
ad5570 rev. c | page 10 of 24 terminology relative accuracy or integral nonlinearity (inl) relative accuracy or integral nonlinearity is a measure of the maximum deviation, in lsbs, from a straight line pass- ing through the endpoints of the dac transfer function. monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital inputs. the ad5570 is mono- tonic over its full operating temperature range. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. gain error gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. it is the deviation in slope of the dac transfer characteristic from the ideal. gain error temperature coefficient gain error temperature coefficient is a measure of the change in gain error with changes in temperature. it is expressed in ppm/c. negative full-scale error/zero scale error negative full-scale error is the error in the dac output voltage when all 0s are loaded into the dac latch. ideally, the output voltage, with all 0s in the dac latch, is ?2 v ref . full-scale error full-scale error is the error in the dac output voltage when all 1s are loaded to the dac latch. ideally, the output voltage with all 1s loaded into the dac latch is 2 v ref ? 1 lsb. bipolar zero error bipolar zero error is the deviation of the analog input from the ideal half-scale output of 0.0000 v when the inputs are loaded with 0x8000. output voltage settling time output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. slew rate the slew rate of a device is a limitation in the rate of change of output voltage. the output slewing speed of a voltage-output dac converter is usually limited by the slew rate of the ampli- fier used at its output. slew rate is measured from 10% to 90% of the output signal and is given in v/s. digital-to-analog glitch impulse digital-to-analog glitch impulse is the amount of charge injected into the analog output when the input codes in the dac register change state. it is specified as the area of the glitch in nv-s and is measured when the digital input code changes by 1 lsb at the major carry transition, that is, from code 0x7fff to 0x8000. bandwidth the reference amplifiers within the dac have a finite band- width to optimize noise performance. to measure it, a sine wave is applied to the reference input (refin), with full-scale code loaded to the dac. the bandwidth is the frequency at which the output amplitude falls to 3 db below the input. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. sync is held high, while the sclk and sdin signals are tog- gled. digital feedthrough is specified in nv-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. power supply sensitivity power supply sensitivity indicates how the output of the dac is affected by changes in the power supply voltage.
ad5570 rev. c | page 11 of 24 typical performance characteristics code inl (lsb) 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 1.0 0.6 0.4 0.8 50k 40k 30k 20k 10k 60k t a = 25c v dd /v ss = 15v refin = +5v 03760-006 figure 6. integral nonlinearity vs. code, v dd /v ss = 15 v code dnl (lsb) 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 1.0 0.6 0.4 0.8 50k 40k 30k 20k 10k 60k t a = 25c v dd /v ss = 15v refin = +5v 03760-007 figure 7. differential nonlinearity vs. code, v dd /v ss = 15 v code inl (lsb) 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 1.0 0.6 0.4 0.8 50k 40k 30k 20k 10k 60k t a = 25c v dd /v ss = 12v refin = +5v 03760-008 figure 8. integral nonlinearity vs. code, v dd /v ss = 12 v code dnl (lsb) 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 1.0 0.6 0.4 0.8 50k 40k 30k 20k 10k 60k t a = 25c v dd /v ss = 12v refin = +5v 03760-009 figure 9. differential nonlinearity vs. code, v dd /v ss = 12 v temperature (c) inl (lsb) ?40 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 1.0 0.8 0.4 0.6 100 806040 20 0 ?20 120 v dd /v ss = 15v refin = +5v 03760-018 figure 10. integral nonlinearity vs. temperature, v dd /v ss = 15 v temperature (c) dnl (lsb) ?40 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 1.0 0.8 0.4 0.6 100 806040 20 0 ?20 120 v dd /v ss = 15v refin = +5v 03760-019 figure 11. differential nonlinearity vs. temperature, v dd /v ss = 15 v
ad5570 rev. c | page 12 of 24 temperature (c) inl (lsb) ?40 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 1.0 0.8 0.4 0.6 10080604020 0 ?20 120 v dd /v ss = 12v refin = +5v 03760-020 figure 12. integral nonlinearity vs. temperature, v dd /v ss = 12 v temperature (c) dnl (lsb) ?40 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 1.0 0.8 0.4 0.6 100 806040 20 0 ?20 120 v dd /v ss = 12v refin = +5v 03760-021 figure 13. differential nonlinearity vs. temperature, v dd /v ss = 12 v supply voltage (v) inl (lsb) 11.4 15.0 14.0 13.0 12.0 16.0 16.5 03760-023 ?1.0 ?0.6 ?0.4 ?0.2 ?0.8 0.2 0.4 0 1.0 0.6 0.8 t a = 25c refin = 5v figure 14. integral nonlinearity vs. supply voltage supply voltage (v) dnl (lsb) 11.4 15.0 14.0 13.0 12.0 16.0 16.5 03760-024 ?1.0 ?0.6 ?0.4 ?0.2 ?0.8 0.2 0.4 0 1.0 0.6 0.8 t a = 25c refin = 5v figure 15. differential nonlinearity vs. supply voltage time (hours) inl (lsb) 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?1.0 ?0.4 ?0.6 ?0.8 0 100 200 300 400 500 700 800 900 600 1000 03760-052 v dd /v ss = 16.5v t a = 125c figure 16. inl drift over time reference voltage (v) inl error (lsb) 2.0 ?1.0 ?0.5 0 0.5 1.0 2.0 1.5 4.5 4.0 3.5 3.0 2.5 5.0 5.5 03760-026 v dd /v ss = 12v t a = 25c figure 17. integral nonlinearity error vs. reference voltage, v dd /v ss = 12 v
ad5570 rev. c | page 13 of 24 reference voltage (v) dnl error (lsb) 2.0 ?0.5 ?0.3 ?0.2 ?0.1 ?0.4 0 0.1 0.2 0.3 0.5 0.4 4.5 4.0 3.5 3.0 2.5 5.0 5.5 03760-027 v dd /v ss = 12v t a = 25c figure 18. differential nonlinearity error vs. reference voltage, v dd /v ss = 12 v reference voltage (v) tue error (lsb) 2.0 ?5.0 ?2.5 0 2.5 5.0 10.0 7.5 4.5 4.0 3.5 3.0 2.5 5.0 5.5 03760-028 v dd /v ss = 15v or 12v t a = 25c figure 19. tue error vs. reference voltage, v dd /v ss = 15 v or 12 v reference voltage (v) inl error (lsb) 2.0 2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 3.53.0 5.0 5.5 6.0 4.54.0 6.5 03760-048 v dd /v ss = 15v t a = 25c figure 20. integral nonlinearity error vs. reference voltage, v dd /v ss = 15 v reference voltage (v) inl error (lsb) 2.0 2.5 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 3.53.0 5.0 5.5 6.0 4.54.0 6.5 03760-049 v dd /v ss = 15v t a = 25c figure 21. integral nonlinearity error vs. reference voltage, v dd /v ss = 15 v v dd /v ss (v) |i ss | i dd /i ss (ma) 11.4 2.0 2.5 3.0 3.5 4.0 5.0 4.5 14.4 13.4 12.4 15.4 16.4 |i dd | t a = 25c refin = 5v 03760-029 figure 22. i dd /i ss vs. v dd /v ss supply voltage (v) i dd /i ss power-down current (a) 11.4 0 5 10 15 25 20 14.4 13.4 12.4 15.4 16.4 |i ss in power-down | |i dd in power-down | t a = 25c refin = +5v 03760-030 figure 23. i dd /i ss in power-down vs. supply voltage
ad5570 rev. c | page 14 of 24 temperature (c) offset error (lsb) ?40 ?10 ?9 ?8 ?7 ?6 ?5 ?4 0 ?1 ?3 ?2 100806040200 ?20 120 03760-031 v dd /v ss = 12v or 15v refin = 5v figure 24. offset error vs. temperature temperature (c) bipolar zero error (lsb) ?40 ?10 ?9 ?8 ?7 ?6 ?5 ?4 0 ?1 ?3 ?2 100 806040 20 0 ?20 120 v dd /v ss = 12v v dd /v ss = 15v refin = +5v 03760-032 figure 25. bipolar zero error vs. temperature temperature (c) gain error (lsb) ?40 ?10 ?8 ?6 ?4 ?2 0 2 10 8 4 6 100 806040 20 0 ?20 120 v dd /v ss = 12v v dd /v ss = 15v refin = +5v 03760-034 figure 26. gain error vs. temperature v logic (v) i dd (ma) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 3.75 3.80 3.85 3.90 3.95 4.00 4.05 4.10 4.15 5.0 03760-035 t a = 25c refin = 5v 15v supplies decreasing increasing 12v supplies increasing decreasing figure 27. supply current vs. logic input current for sclk, sync , sdin, and ldac increasing and decreasing ?10 ?4 ?6 ?8 4 2 0 ?2 11 10 8 6 1s/div v dd = +15v v ss = ?15v refin = +5v t a = 25c 03760-046 time (s) v out (v) figure 28. settling time capacitance (nf) time (s) 0123456789 0 5 10 15 20 25 30 35 40 9.4 t a = 25c refin = +5v v dd /v ss = 12v v dd /v ss = 15v 03760-037 figure 29.14-bit settling time vs. load capacitance
ad5570 rev. c | page 15 of 24 sink current (ma) source current (ma) output voltage (v) ?10?8?6?4?202468 9.9952 9.9955 9.9958 9.9961 9.9964 9.9967 9.9970 9.9973 9.9976 9.9979 9.9982 9.9985 9.9988 9.9991 9.9994 9.9997 10.0000 10 03760-038 15v supplies 12v supplies t a = 25c refin = 5v 1s/div voltage (v) ?0.072 ?0.067 ?0.062 ?0.057 ?0.052 ?0.047 ?0.042 ?0.037 ?0.032 ?0.027 ? 0.022 v dd = +12v v ss = ?12v refin = +5v t a = 25c 8000 7fffh 0 3760-051 figure 30. source and sink capability of output amplifier with full-scale loaded figure 33. major code transition glitch energy, v dd /v ss = 12 v output voltage (v) ?10?8?6?4?202468 ?10.0000 ?9.9997 ?9.9994 ?9.9991 ?9.9988 ?9.9985 ?9.9982 ?9.9979 ?9.9976 ?9.9973 10 03760-039 12v supplies 15v supplies sink current (ma) source current (ma) t a = 25c refin = 5v ch1 20v/div 20s/pt m 1.0 ? ms 500ks/s a ch1 0.0v v dd = +15v v ss = ?15v midscale loaded 20v/div v refin = 0v 03760-047 figure 31. source and sink capability of output amplifier with zero-scale loaded figure 34. peak-to-peak noise (100 khz bandwidth) v dd = +15v v ss = ?15v refin = +5v t a = 25c ramp time = 100s v dd /v ss = 10v/div v out = 10mv/div 100s/div v out v ss v dd 03760-042 1s/div v out (v) ?0.10 ?0.09 ?0.08 ?0.07 ?0.06 ? 0.05 v dd = +15v v ss = ?15v refin = +5v t a = 25c 7 fff 8000h 03760-040 figure 32. major code transition glitch energy, v dd /v ss = 15 v figure 35. v out vs. v dd /v ss on power-up
ad5570 rev. c | page 16 of 24 general description the ad5570 is a single 16-bit serial input, voltage output dac. it operates from supply voltages of 11.4 v to 16.5 v, and has a buffered voltage output of up to 13.6 v. data is written to the ad5570 in a 16-bit word format, via a 3-wire serial interface. the device also offers an sdo pin, available for daisy-chaining or readback. the ad5570 incorporates a power-on reset circuit to ensure the dac output powers up to 0 v. the device also has a power-down pin to reduce the typical current consumption to 16 a. dac architecture the dac architecture of the ad5570 consists of a 16-bit, current- mode, segmented r-2r dac. the simplified circuit diagram for the dac section is shown in figure 36 . the four msbs of the 16-bit data word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of the 15 matched resistors to either agnd or iout. the remaining 12 bits of the data word drive switches s0 to s11 of the 12-bit r-2r ladder network. 2r e15 v ref 2r e14 e1 2r s11 rr r 2r s10 2r 12-bit r-2r ladder v out 2r s0 2r agnd iout r/8 4 msbs decoded into 15 equal segments 03760-010 figure 36. dac ladder structure reference buffers the ad5570 operates with an external reference. the reference input (refin) has an input range of up to 7 v. this input voltage is then used to provide a buffered positive and negative reference for the dac core. the positive reference is given by refin ref vv =+ 2 and the negative reference to the dac core is given by refin ref vv =? 2 these positive and negative reference voltages define the dac output range. serial interface the ad5570 is controlled over a versatile 3-wire serial interface that operates at clock rates up to 10 mhz and is compatible with spi, qspi, microwire, and dsp interface standards. input shift register the input shift register is 16 bits wide. data is loaded into the device as a 16-bit word under the control of a serial clock input, sclk. the timing diagram for this operation is shown in figure 2 . on power-up, the input shift register and dac register are loaded with midscale (0x8000). the dac coding is straight binary; all 0s produce an output of ?2 v ref ; all 1s produce an output of +2 v ref ? 1 lsb. the sync input is a level-triggered input that acts as a frame synchronization signal and chip enable. sync must frame the serial word being loaded into the device. data can be transferred into the device only while sync is low. to start the serial data transfer, sync is taken low, observing the minimum sync to sclk falling edge setup time, t 4 . after sync goes low, serial data on sdin is shifted into the devices input shift register on the falling edges of sclk. sync can be taken high after the falling edge of the 16 th sclk pulse, observing the minimum sclk falling edge to sync rising edge time, t 7 . after the end of the serial data transfer, data is automatically transferred from the input shift register to the input register of the dac. when data has been transferred into the input register of the dac, the dac register and dac output can be updated by taking ldac low while sync is high. load dac input ( ldac ) there are two ways that the dac register and dac output can be updated when data has been transferred into the input register of the dac. depending on the status of both sync and ldac , one of two update modes is selected. the first mode is synchronous ldac . in this mode, ldac is low while data is being clocked into the input shift register. the dac output is updated when sync is taken high. the update here occurs on the rising edge of sync . the second mode is asynchronous ldac . in this mode, ldac is high while data is being clocked in. the dac output is updated by taking ldac low any time after sync has been taken high. the update now occurs on the falling edge of ldac . figure 37 shows a simplified block diagram of the input loading circuitry. v out dac register input shift register output i/v amplifier ldac sdo sdin 16-bit dac v refin sync 03760-012 figure 37. simplified serial interface showing input loading circuitry
ad5570 rev. c | page 17 of 24 transfer function table 6 shows the ideal input code to the output voltage rela- tionship for the ad5570. table 6. binary code table digital input msb lsb analog output (v out ) 1111 1111 1111 1111 +2 v ref (32,767/32,768) 1000 0000 0000 0001 +2 v ref (1/32,768) 1000 0000 0000 0000 0 v 0111 1111 1111 1111 ?2 v ref (1/32,768) 0000 0000 0000 0000 ?2 v ref the output voltage expression is given by ]65536/[42 dv vv refin refin out +?= where: d is the decimal equivalent of the code loaded to the dac. v refin is the reference voltage available at the refin pin. clear ( clr ) clr is an active low digital input that allows the output to be cleared to 0 v. when the clr signal is brought back high, the output stays at 0 v until ldac is brought low. the relationship between ldac and clr is explained further in . tabl e 7 table 7. relationships among pd , clr , and ldac pd clr ldac comments 0 x x pd has priority over ldac and clr . the output remains at 0 v through an internal 20 k resistor. it is still possible to address both the input register and dac register when the ad5570 is in power-down. 1 0 0 data is written to the input register and dac register. clr has higher priority over ldac ; therefore, the output is at 0 v. 1 0 1 data is written to the input register only. the output is at 0 v and remains at 0 v when clr is taken back high. 1 1 0 data is written to the input register and the dac register. the output is driven to the dac level. 1 1 1 data is written to the input register only. the output of the dac register is unchanged. power-down ( pd ) the power-down pin allows the user to place the ad5570 into a power-down mode. in power-down mode, power consump- tion is at a minimum; the device typically consumes only 16 a. power-on reset the ad5570 contains a power-on reset circuit that controls the output during power-up and power-down. this is useful in appli- cations where the known state of the output of the dac during power-up is important. on power-up and power-down, the output of the dac and v out , is held at agnd. serial data output (sdo) the sdo is the internal shift registers output. for the ad5570, sdo is an internal pull-down only; an external pull-up resistor of ~5 k to external logic high is required. sdo pull-down is disabled when the device is in power-down, thus saving current. the availability of sdo allows any number of ad5570s to be daisy-chained together. it also allows for the contents of the dac register, or any number of dacs daisy-chained together, to be read back for diagnostic purposes. daisy chaining this mode of operation is designed for multi dac systems, where several ad5570s can be connected in cascade as shown in figure 38 . this is done by connecting the control inputs in parallel and then daisy-chaining the sdin and sdo i/os of each device. an external pull-up resistor of ~5 k on sdo is required when using the part in daisy-chain mode. as described earlier, when sync goes low, serial data on sdin is shifted into the input shift register on the falling edge of sclk. if more than 16 clock pulses are applied, the data ripples out of the shift resister and appears on the sdo line. by connecting this line to the sdin input on the next ad5570 in the chain, a multi dac interface can be constructed. one data transfer cycle of 16 sclk pulses is required for each dac in the system. therefore, the total number of clock cycles must equal 16 n, where n is the total number of devices in the chain. the first data transfer cycle written into the chain appears at the last dac in the system on the final data transfer cycle. when the serial transfer to all devices is complete, take sync high. this prevents any further data from being clocked into the devices. a continuous sclk source can be used if sync is held low for the correct number of clock cycles. alternatively, a burst clock containing the exact number of clock cycles can be used and sync is taken high some time later. the outputs of all the dacs in the system can be updated simultaneously using the ldac signal.
ad5570 rev. c | page 18 of 24 readback the ad5570 allows the data contained in the dac register to be read back, if required. as with daisy chaining, an external pull-up resistor of ~5 k on sdo is required. the data in the dac register is available on sdo on the falling edges of sclk when sync is low. on the 16 th sclk edge, sdo is updated to repeat sdin with a delay of 16 clock cycles. to read back the contents of the dac register without writing to the part, take sync low while ldac is held high. daisy-chaining readback is also possible through the sdo pin of the last device in the dac chain because the dac data passes through the dac chain with the appropriate latency. 68hc11* miso sync sdin sclk mosi sck pc7 pc6 ldac sdo sync sclk ldac sdo sync sclk ldac sdo sdin sdin *additional pins omitted for clarity. ad5570* ad5570* ad5570* v logic r r r 03760-013 figure 38. daisy-chaining using the ad5570
ad5570 rev. c | page 19 of 24 applications information typical operating circuit figure 39 shows the typical operating circuit for the ad5570. the only external component needed for this precision 16-bit dac is a single external positive reference. because the device incorporates reference buffers, it eliminates the need for a negative reference, external inverters, precision amplifiers, and resistors. this leads to an overall savings of both cost and board space. in the circuit shown in figure 39 , v dd and v ss are both connected to 15 v, but v dd and v ss can operate supplies from 11.4 v to 16.5 v. agnds is connected to agnd, but the option of force/ sense is included on this device if required by the user. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad5570 v ss v dd clr ldac sync sclk sdin sdo refgnd refin refgnd v out agnds agnd pd dgnd +15v 0.1f 10f 0.1f 10f ?15v v out 5v adr435 ldac sync sclk sdin sdo 5k? 0 3760-044 figure 39. typical operating circuit force/sense of agnd because of the extremely high accuracy of this device, system design issues (such as grounding and contact resistance) are very important. the ad5570, with 10 v output, has an lsb size of 305 v. therefore, series wiring and connector resistances of very small values can cause voltage drops of an lsb. for this reason, the ad5570 offers a force/sense output configuration. figure 40 shows how to connect the ad5570 to the force/sense amplifier. where accuracy of the output is important, an ampli- fier such as the op177 is ideal. the op177 is ultraprecise with offset voltages of 10 v maximum at room temperature, and off- set drift of 0.1 v/c maximum. alternative recommended amplifiers are the op1177 and the op77. for applications where optimization of the circuit for se ttling time is needed, the ad845 is recommended. precision voltage reference selection to achieve the optimum performance from the ad5570, give special attention to the selection of a precision voltage reference. the ad5570 has just one reference input, refin. this voltage on refin is used to provide a buffered positive and negative reference for the dac core. therefore, any error in the voltage reference is reflected in the output of the device. 6 2 3 (other connections omitted for clarity) op177* *for optimum settling time performance, the ad845 is recommended. 03760-045 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad5570 v ss v dd clr ldac sync sclk sdin sdo refgnd refin refgnd v out agnds agnd pd dgnd figure 40. driving agnd and agnds using a force/sense amplifier the four possible sources of error to consider when choosing a voltage reference for high accuracy applications are initial accuracy, long-term drift, temperature coefficient of the out- put voltage, and output voltage noise. initial accuracy on the output voltage of an external reference can lead to a full-scale error in the dac. therefore, to minimize these errors, a reference with low initial accuracy specification is preferred. also, choosing a reference with an output trim adjust- ment, such as the adr425, allows a system designer to trim out system errors by setting the reference voltage to a voltage other than the nominal. the trim adjust ment can also be used at tem- perature to trim out any error. long-term drift (ltd) is a measure of how much the reference drifts over time. a reference with a tight long-term drift specifica- tion ensures that the overall solution remains relatively stable over its entire lifetime. the temperature coefficient of a references output voltage affects inl, dnl, and tue. choose a reference with a tight temperature coefficient specification to reduce the depend ence of the dac output voltage on ambient conditions. in high accuracy applications that have a relatively low noise budget, reference output voltage noise needs to be considered. it is important to choose a reference with as low an output noise voltage as practical for the system resolution required. precision voltage references, such as the adr435 (xfet? design), produce low output noise in the 0.1 hz to 10 hz region. however, as the circuit bandwidth increases, filtering the output of the reference can be required to minimize the output noise.
ad5570 rev. c | page 20 of 24 table 8. partial list of prec ision references recommended for use with the ad5570 part no. initial accuracy (mv max) long-term drift (ppm typ) temp drift (ppm/ c max) 0.1 hz to 10 hz noise (v p-p typ) adr435 6 30 3 3.4 adr425 6 50 3 3.4 adr02 1 5 50 3 15 adr395 6 50 25 5 ad586 2.5 15 10 4 1 available in sc70 package. layout guidelines in any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board that the ad5570 is mounted on is designed so the analog and dig- ital sections are separated and confined to certain areas of the board. if the ad5570 is in a system where multiple devices require an agnd-to-dgnd connection, the connection is made at one point only. the star ground point is established as close as possible to the device. the ad5570 has ample supply bypassing of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor has low effective series resistance (esr) and effective series inductance (esi) such as the common ceramic types that provide a low imped- ance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad5570 use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks are shielded with digital ground to avoid radiating noise to other parts of the board, and are never be run near the refer- ence inputs. a ground line routed between the sdin and sclk lines reduces crosstalk between them; this is not required on a multilayer board that has a separate ground plane, but separating the lines helps. it is essential to minimize noise on the refin line because it couples through to the dac output. avoid crossover of digital and analog signals. traces on opposite sides of the board must run at right angles to each other. this reduces the effects of feed through the board. a micro- strip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. opto-isolators in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled. opto-isolators provide voltage isolation in excess of 3 kv. the serial loading structure of the ad5570 makes it ideal for opto-isolated interfaces, because the number of interface lines is kept to a minimum. figure 41 shows a 4-channel isolated inter- face to the ad5570. to reduce the number of opto-isolators, the ldac pin can be tied permanently low if the simultaneous updating of the dac is not required. the dac can then be updated on the rising edge of sync . v cc to sdin to sclk to sync sync out serial clock out serial data out controller opto-coupler to ldac control out 03760-050 figure 41. opto-isolated interface
ad5570 rev. c | page 21 of 24 microprocessor interfacing microprocessor interfacing to the ad5570 is via a serial bus that uses standard protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. the ad5570 requires a 16-bit data word with data valid on the falling edge of sclk. for all the interfaces, the dac output update can be done auto- matically when all the data is clocked in, or it can be done under the control of ldac . the contents of the dac register can be read using the readback function. ad5570 to mc68hc11 interface figure 42 shows an example of a serial interface between the ad5570 and the mc68hc11 microcontroller. the serial periph- eral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1), clock polarity bit (cpol = 0), and the clock phase bit (cpha = 1). the spi is configured by writing to the spi control register (spcr); see documentation on the mc68hc11. sck of the mc68hc11 drives the sclk of the ad5570, the mosi output drives the serial data line (sdin) of the ad5570, and the miso input is driven from sdo. the sync is driven from one of the port lines, in this case, pc7. when data is being transmitted to the ad5570, the sync line (pc7) is taken low and data is transmitted msb first. data appear- ing on the mosi output is valid on the falling edge of sck. eight falling clock edges occur in the transmit cycle; therefore, in order to load the required 16-bit word, pc7 is not brought high until the second 8-bit word has been transferred to the dacs input shift register. ad5570* sclk sdin sync mosi sclk pc7 mc68hc11* *additional pins omitted for clarity. sdo miso 03760-014 figure 42. ad5570 to mc68hc11 interface ldac is controlled by the pc6 port output. the dac can be updated after each 2-byte transfer by bringing ldac low. this example does not show other serial lines for the dac. if clr were used, control it by the port output pc5. ad5570 to 8xc51 interface the ad5570 requires a clock synchronized to the serial data. for this reason, the 8xc51 must be operated in mode 0. in this mode, serial data enters and exits through rxd, and a shift clock is output on txd. p3.3 and p3.4 are bit-programmable pins on the serial port and are used to drive sync and ldac , respectively. the 8xc51 provides the lsb of its sbuf register as the first bit in the data stream. the user must ensure that the data in the sbuf register is arranged correctly because the dac expects msb first. ad5570* sclk sdin sync txd p3.3 8xc51* *additional pins omitted for clarity. rxd ldac p3.4 03760-015 figure 43. ad5570 to 8xc51 interface when data is to be transmitted to the dac, p3.3 is taken low. data on rxd is clocked out of the microcontroller on the rising edge of txd and is valid on the falling edge. as a result, no glue logic is required between this dac and the microcontroller interface. the 8xc51 transmits data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. because the dac expects a 16-bit word, sync (p3.3) must be left low after the first eight bits are transferred. after the second byte has been trans- ferred, the p3.3 line is taken high. the dac can be updated using ldac via p3.4 of the 8xc51.
ad5570 rev. c | page 22 of 24 ad5570 to adsp21xx an interface between the ad5570 and the adsp21xx family is shown in figure 44 . the adsp21xx must be set up to operate in the sport transmit alternate framing mode. the adsp21xx is programmed through the sport control register and is con- figured as follows: internal clock operation, active low framing, and 16-bit word length. transmission is initiated by writing a word to the tx register, after the sport has been enabled. as the data is clocked out of the dsp on the rising edge of sclk, no glue logic is required to inter- face the dsp to the dac. in the interface shown, the dac output is updated using the ldac pin via the dsp. alternatively, the ldac input can be tied permanently low, and then the update is automatic when tfs is taken high. ad5570* sclk sdin sync dt sclk rfs adsp21xx *additional pins omitted for clarity. sdo dr tfs ldac fo 03760-016 figure 44. ad5570 to adsp21xx interface ad5570 to pic16c6x/7x the pic16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit set to 0. this is done by writing to the synchronous serial port control register, sspcon (see documentation on the pic16/17 microcontroller). in this example, i/o port ra1 is being used to pulse sync and enable the serial port of the ad5570. this microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive write operations are needed. shows the connection diagram. figure 45 ad5570* sclk sdin sync sdo/rc5 sclk/rc3 ra1 pic16c6x/7x* * additional pins omitted for clarity. sdo sdi/rc4 03760-017 figure 45. ad5570 to pic16c6x/7x interface evaluation board the ad5570 comes with a full evaluation board to aid designers in evaluating the high performance of the part with minimal effort. the evaluation board requires a power supply, a pc, and an oscilloscope. the ad5570 evaluation kit includes a populated and tested ad5570 printed circuit board. the evaluation board inter- faces to the parallel interface of a pc. software is available with the evaluation board that allows the user to easily pro- gram the ad5570. a schematic of the evaluation board is shown in figure 46 . the software runs on any pc installed with microsoft? windows? 95/ windows? 98/windows? me/ windows? 2000/windows? xp. an application note containing full details on operating the evaluation board comes supplied with the ad5570 evalua- tion board.
ad5570 rev. c | page 23 of 24 j11?19 j11?12 j11?4 j11?6 j11?7 j11?8 j11?13 j11 ? centronics connector j11?3 j11?2 j11?5 j4 j5 j6 j7 j8 j9 j10 j11?10 j11?9 j13?1 + + + + ++++ c30 10f 20v c12 10f c11 10f + c13 10f + c21 10f + c22 10f c23 0.1f c24 0.1f c15 0.1f c10 10f c9 10f c8 0.1f c7 0.1f c6 0.1f c14 0.1f 0.33f c2 c4 0.01f c36 0.1f c3 0.1f c35 0.1f c16 0.1f c34 10f c5 10f r2 10k? r3 10k? c17 0.1f c18 10f u5 u3 u1 u2 j1 tp5 v out c1 r1 ref/2 ref/2 op v+ v ? white plastic ssop clamp op177 adr435 ad5570 c31 0.1f c32 0.1f c33 0.1f dgnd dgnd dvdd dvdd j13?2 j12?1 j12?2 j11?20 j11?21 j11?22 j11?23 j11?24 j11?25 j11?26 j11?27 j11?28 j11?29 j11?30 avdd avdd avdd v ss avdd dvdd avdd lk2 lk1 tp4 tp10 tp7 tp1tp2tp9tp3tp8 j2 lk3 vss agnd dgnd avdd avdd y0 v in sclk pd sdo sdin sclk sync ldac clr v dd v dd refin v ss refin lk5 gnd dgnd agnds agnd refgnd refgnd sdata busy gnd4 u6 gnd3 v out v in v out v out +v in trim gnd 4 gnd2 gnd1 9 8 7 6 5 1 2 3 3 2 2 912 12 15 62 5 11 16 14 13 3 7 6 4 18 4 5 6 7 10 8 7 6 5 4 3 4 7 5 3 11 19 13 15 17 y1 y2 y3 a0 a1 a2 a3 agnd v ss 74act244 lm78l05acm ad7895-10 u4?b agnd j12?3 v ss oe y0 18 16 14 12 2 1 4 6 8 y1 y2 y3 a0 a1 a2 a3 74act244 u4?a oe 2 1 4 6 8 18 16 14 12 y0 y1 y2 y3 a0 a1 a2 a3 74act244 u9?a oe 11 19 13 15 17 9 7 5 3 y0 y1 y2 y3 a0 a1 a2 a3 74act244 u9?b sdo din sclk sclk_adc sdata_adc data sclk din dout oe ref/2 ref ref convst clr pd convst ldac sync r4 4.7k ? dvdd r5 4.7k ? r7 4.7k ? r6 4.7k ? dvdd dvdd lk4 pd ldac sync clr 03760-043 figure 46. evaluation board schematic
ad5570 rev. c | page 24 of 24 outline dimensions compliant to jedec standards mo-150-ac 060106-a 16 9 8 1 6.50 6.20 5.90 8.20 7.80 7.40 5.60 5.30 5.00 seating plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarity 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 47. 16-lead shrink small outline package [ssop] (rs-16) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad5570ars ?40c to +85c 16-lead ssop rs-16 ad5570ars-reel ?40c to +85c 16-lead ssop rs-16 ad5570ars-reel7 ?40c to +85c 16-lead ssop rs-16 ad5570arsz ?40c to +85c 16-lead ssop rs-16 ad5570arsz-reel ?40c to +85c 16-lead ssop rs-16 ad5570arsz-reel7 ?40c to +85c 16-lead ssop rs-16 ad5570brs ?40c to +85c 16-lead ssop rs-16 ad5570brs-reel ?40c to +85c 16-lead ssop rs-16 ad5570brs-reel7 ?40c to +85c 16-lead ssop rs-16 ad5570brsz ?40c to +85c 16-lead ssop rs-16 ad5570brsz-reel ?40c to +85c 16-lead ssop rs-16 ad5570brsz-reel7 ?40c to +85c 16-lead ssop rs-16 ad5570wrs ?40c to +125c 16-lead ssop rs-16 AD5570WRSZ ?40c to +125c 16-lead ssop rs-16 AD5570WRSZ-reel ?40c to +125c 16-lead ssop rs-16 AD5570WRSZ-reel7 ?40c to +125c 16-lead ssop rs-16 ad5570yrs ?40c to +125c 16-lead ssop rs-16 ad5570yrs-reel ?40c to +125c 16-lead ssop rs-16 ad5570yrs-reel7 ?40c to +125c 16-lead ssop rs-16 ad5570yrsz ?40c to +125c 16-lead ssop rs-16 ad5570yrsz-reel ?40c to +125c 16-lead ssop rs-16 ad5570yrsz-reel7 ?40c to +125c 16-lead ssop rs-16 eval-ad5570ebz evaluation board 1 z = rohs compliant part. ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03760-0-11/10(c)

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